William Holt  Executive Vice PresidentGeneral Manager, Technology and Manufacturing Group 

 

 Intel Continues to Deliver the Benefits of Moore’s Law  Key Messages from 2013  True Cost Reduction Remains Possible in a Capital Intensive Environment  The Benefits of Technology Apply Across the Product Portfolio 

 

 14nm Status - 2013  Reliability Scorecard at the same point in development  Module  22nm (2 year offset)  14nm  Transistor        Interconnect        Thermo-Mechanical/Moisture        Test Vehicle Yield        ESD/LU        Alpha Particle/Soft Error        Low risk    Meeting all cert goals    Medium risk  Close to meeting goals   High risk    Not yet meeting all goals, needs additional work  Source: Intel. * Forecast  Generally healthy reliability at this stage, on track for Q1 ’14 certification *      Yieldat the same point in development  May  June  July  Aug  Sept  Oct  Nov  Dec  Jan  Feb      Key Parameter Matching% of key process parameters meeting 3-sigma targetsat the same point in development  22nm  14nm  14 nm key process parameter matching on track with 22 nm trend  Weeks      Performance ImprovementSwitching Energy vs. Gate Delay    22nm  14nm  Switching Energy Change (%)  Delay Change (%)  14nm  22nm  Increasing Yield  Increasing Matching  Better  Yield rapidly increasing, on track for matched yield in Q1 ’14 *  ≈ 

 

     Reliability Scorecard at the same point in development    Performance ImprovementSwitching Energy vs. Gate Delay  Increasing Yield  14nm  22nm  Yield is now in healthy range with further improvements coming  ≈    22nm  14nm  Switching Energy Change (%)  Delay Change (%)  14nm Status - 2014  Reliability Scorecard at the same point in development  Module  22nm (2 year offset)  14nm  Transistor        Interconnect        Thermo-Mechanical/Moisture        Test Vehicle Yield        ESD/LU        Alpha Particle/Soft Error        Low risk    Meeting all cert goals    Medium risk  Close to meeting goals   High risk    Not yet meeting all goals, needs additional work  14nm PRQ achieved Q2 2014    Increasing Matching  Key Parameter Matching% of key process parameters meeting 3-sigma targetsat the same point in development  22nm  14nm  14 nm key process parameter matching on track with 22 nm trend  Weeks      Better  Yieldat the same point in development  May  June  July  Aug  Sept  Oct  Nov  Dec  Jan  Feb  Mar  Apr  May  Jun  Source: Intel  

 

 14 nm Product Yield Is In Healthy Range  Increasing Yield  14nm Broadwell Yield Trend  22 nm data are shifted to align date of lead product qualDepicts relative health, lines not to scale  22nm Is Intel’s Highest Yielding Process Ever                                  14 nm  22 nm  Forecast  PRQ        Q1 ‘14    Q2 ‘14    Q3 ‘14    Q4 ‘14    Q1 ‘15  Broadwell SoC    Source: Intel  

 

         14nm Technology Overview   A True 14 nm Technology 2nd Generation FinFET 52 nm Interconnect Pitch First Use of Air Gaps 

 

  22 nm 14 nm Node Node ScaleTransistor Fin Pitch 60 42 .70xTransistor Gate Pitch 90 70 .78xInterconnect Pitch 80 52 .65x nm nm  Intel Has Developed a True 14 nm Technology   

 

 14 nm Design Rules + 2nd Generation Tri-gate Transistor Provides Industry-leading SRAM Density   SRAM Memory Cells  .108 um2(Used on CPU products)  .0588 um2(0.54x area scaling)  22 nm Process  14 nm Process 

 

 Transistor Fin Improvement  22 nm Process            Si Substrate  60 nmpitch  34 nmheight        14 nm Process      Si Substrate             

 

 Tighter Fin Pitch for Improved Density   Transistor Fin Improvement            Si Substrate  42 nmpitch                  Si Substrate  60 nmpitch  34 nmheight        22 nm Process  14 nm Process 

 

 Taller and Thinner Fins for Increased Drive Current and Performance   Transistor Fin Improvement            Si Substrate  42 nmpitch  42 nmheight                  Si Substrate  60 nmpitch  34 nmheight        22 nm Process  14 nm Process 

 

 Transistor Fin Improvement  Reduced Number of Fins for Improved Density and Lower Capacitance           Si Substrate  42 nmpitch  42 nmheight                Si Substrate  60 nmpitch  34 nmheight        22 nm Process  14 nm Process 

 

 Transistor Fin Improvement   22 nm 1st Generation Tri-gate Transistor   14 nm 2nd Generation Tri-gate Transistor                      Metal Gate                        Si Substrate  Metal Gate      Si Substrate 

 

 Transistor Fin Improvement   22 nm 1st Generation Tri-gate Transistor   14 nm 2nd Generation Tri-gate Transistor  Source: Intel  

 

         Intel Transistor Leadership                                Projected      TSMCGlobalFoundriesSamsungIBM  3 Years   ‘03 ‘04 ‘05 ‘06 ‘07 ‘08 ‘09 ‘10 ‘11 ‘12 ‘13 ‘14 ‘15 ‘16 ’17 ‘18   ‘03 ‘04 ‘05 ‘06 ‘07 ‘08 ‘09 ‘10 ‘11 ‘12 ‘13 ‘14 ‘15 ‘16 ’17 ‘18        SiGe Strained Silicon  Tri-Gate  High-k Metal Gate  3.5 Years  ~3.5 Years        SiGe Strained Silicon  High-k Metal Gate  Tri-Gate  *Other names and brands may be claimed as the property of others.Source: Dates are based on start of high volume production. Projected dates are based on other company public statements.  

 

       Active Power(Includes performance increase)  Generation  1x  .25x  22 nm  32 nm  45 nm  14 nm  Server LaptopMobile  2nd Generation Tri-Gate is the Critical Enabler  Active Power(Includes performance increase)  Performance per Watt  Performance  22 nm  32 nm  45 nm  14 nm  Generation  Performance   1x  Laptop   Mobile   2x  Server   Performance per Watt  Generation  22 nm  32 nm  45 nm  14 nm  1x  10x  Performance Improved  Active Power Reduced  Performance per Watt Improves  14 nm BDW-Y Delivers >2x Improvement in Performance per Watt  Source: Intel  Server   Laptop   Mobile     >2x  Intel Core M processor 

 

 Interconnects  52 nm Interconnect Pitch Provides Better-than-normal Interconnect Scaling  80 nm minimum pitch  52 nm (0.65x) minimum pitch  22 nm Process  14 nm Process  Source: Intel  

 

 Interconnects  52 nm Interconnect Pitch Provides Better-than-normal Interconnect Scaling  80 nm minimum pitch  52 nm (0.65x) minimum pitch  22 nm Process  14 nm Process  Source: Intel  

 

 Interconnects  52 nm Interconnect Pitch Provides Better-than-normal Interconnect Scaling  80 nm minimum pitch  52 nm (0.65x) minimum pitch  22 nm Process  14 nm Process  First Use of Air Gaps to Improve Interconnect Performance                  Source: Intel  

 

 Logic Area Scaling Trend(Publicly available scaling information)   Gate Pitch x Metal Pitch (nm2)  Start of Volume Production  45nm: K-L Cheng (TSMC), 2007 IEDM, p. 243 28nm: F. Arnaud (IBM alliance), 2009 IEDM, p. 65120nm: H. Shang (IBM alliance), 2012 VLSI, p.12916nm: S. Wu (TSMC), 2013 IEDM, p. 22410nm: K-I Seo (IBM alliance), 2014 VLSI, p. 14  Others based on published information:    Source: Intel data from shipping products                                          Logic  Cell   Height  Logic Cell   Width    Gate   Pitch  Metal   Pitch    Projected 

 

 14nm Enables Cost and Performance Benefits    Broadwell 2 X 2 (14nm)1.3B transistors  Haswell 2 X 2 (22nm)960M Transistors  37% Smaller  35% More Transistors  Broadwell delivers:2.2x increase in transistor densityUp to 40% better 3D graphics perf1 Enables <9mm fanless designs  Industry’s First 14 nm Processor in Volume Production  1 Intel® Core™ M-5Y70 processor compared to Intel® Core™ i5-4302Y processor 

 

 * Forecast  X      mm2/transistor  Normalized Area/Transistor Growth (mm2/transistor)  65 nm  45 nm  32 nm  22 nm  14 nm  10 nm*  90 nm  0.13 um  =      $/transistor  Normalized Cost per Transistor ($/transistor)  65 nm  45 nm  32 nm  22 nm  14 nm  10 nm*  90 nm  0.13 um       $/mm2  Normalized Capital Growth ($/mm2)  65 nm  45 nm  32 nm  22 nm  14 nm  10 nm*  90 nm  0.13 um  Cost Reduction On Track  Source: Intel  

 

 * Forecast  X      mm2/transistor  Normalized Area/Transistor Growth (mm2/transistor)  65 nm  45 nm  32 nm  22 nm  14 nm  10 nm*  90 nm  0.13 um  =      $/transistor  Normalized Cost per Transistor ($/transistor)  65 nm  45 nm  32 nm  22 nm  14 nm  10 nm*  90 nm  0.13 um       $/mm2  Normalized Capital Growth ($/mm2)  65 nm  45 nm  32 nm  22 nm  14 nm  10 nm*  90 nm  0.13 um  Cost Reduction On Track   7 nm*  Source: Intel  

 

 Intel Continues to Deliver Moore’s Law  Summary  True Cost Reduction Remains Possible  Technology Enables Real Product Improvements  

 

 Legal Disclaimers  Software and workloads used in performance tests may have been optimized for performance only on Intel microprocessors. Performance tests, such as SYSmark and MobileMark, are measured using specific computer systems, components, software, operations and functions. Any change to any of those factors may cause the results to vary.  You should consult other information and performance tests to assist you in fully evaluating your contemplated purchases, including the performance of that product when combined with other products. Intel technologies may require enabled hardware, specific software, or services activation. Check with your system manufacturer or retailer.Tests document performance of components on a particular test, in specific systems. Differences in hardware, software, or configuration will affect actual performance. Consult other sources of information to evaluate performance as you consider your purchase.  For more complete information about performance and benchmark results, visit http://www.intel.com/benchmarks  All dates, forecasts and products specified in this presentation are subject to change without notice.  This presentation will not be updated to reflect any such changes. Copyright 2014 Intel Corporation. *Other names and brands may be claimed as the property of others. 

 

 Risk Factors  The statements in the presentations and other commentary that refer to plans and expectations for the fourth quarter, the year and the future are forward-looking statements that involve a number of risks and uncertainties. Words such as “anticipates,” “expects,” “intends,” “plans,” “believes,” “seeks,” “estimates,” “may,” “will,” “should” and their variations identify forward-looking statements. Statements that refer to or are based on projections, uncertain events or assumptions also identify forward-looking statements. Many factors could affect Intel’s actual results, and variances from Intel’s current expectations regarding such factors could cause actual results to differ materially from those expressed in these forward-looking statements. Intel presently considers the following to be important factors that could cause actual results to differ materially from the company’s expectations.  Demand for Intel’s products is highly variable and could differ from Intel’s expectations due to factors including changes in the business and economic conditions; consumer confidence or income levels; customer acceptance of Intel’s and competitors’ products;  competitive and pricing pressures, including actions taken by competitors; supply constraints and other disruptions affecting customers; changes in customer order patterns including order cancellations; and changes in the level of inventory at customers.Intel’s gross margin percentage could vary significantly from expectations based on capacity utilization; variations in inventory valuation, including variations related to the timing of qualifying products for sale; changes in revenue levels; segment product mix; the timing and execution of the manufacturing ramp and associated costs; excess or obsolete inventory; changes in unit costs; defects or disruptions in the supply of materials or resources; and product manufacturing quality/yields.  Variations in gross margin may also be caused by the timing of Intel product introductions and related expenses, including marketing expenses, and Intel’s ability to respond quickly to technological developments and to introduce new features into existing products, which may result in restructuring and asset impairment charges. Intel operates in highly competitive industries and its operations have high costs that are either fixed or difficult to reduce in the short term.  The declaration and rate of dividend payments and the amount and timing of Intel’s stock buyback program are at the discretion of Intel’s board of directors, and plans for future dividends and stock buy backs and could be affected by changes in Intel’s priorities for the use of cash, such as operational spending, capital spending, acquisitions, and because of changes to Intel’s cash flows and changes in tax laws.Intel’s expected  tax rate is based on current tax law and current expected income and may be affected by the jurisdictions in which profits are determined to be earned and taxed; changes in the estimates of credits, benefits and deductions; the resolution of issues arising from tax audits with various authorities, including payment of interest and penalties; and the ability to realize deferred tax assets.  Gains or losses from equity securities and interest and other could vary from expectations depending on gains or losses on the sale, exchange, change in the fair value or impairments of debt and equity investments; interest rates; cash balances; and changes in fair value of derivative instruments. Intel's results could be affected by adverse economic, social, political and physical/infrastructure conditions in countries where Intel, its customers or its suppliers operate, including military conflict and other security risks, natural disasters, infrastructure disruptions, health concerns and fluctuations in currency exchange rates.  Intel’s results could be affected by the timing of closing of acquisitions, divestitures and other significant transactions.Intel's results could be affected by adverse effects associated with product defects and errata (deviations from published specifications), and by litigation or regulatory matters involving intellectual property, stockholder, consumer, antitrust, disclosure and other issues. An unfavorable ruling could include monetary damages or an injunction prohibiting Intel from manufacturing or selling one or more products, precluding particular business practices, impacting Intel’s ability to design its products, or requiring other remedies such as compulsory licensing of intellectual property.A detailed discussion of these and other factors that could affect Intel’s results is included in Intel’s SEC filings, including the company’s most recent Form 10-Q, Form 10-K and earnings release. 

 

 Configuration Information  Intel® Core™ M-5Y70 Processor (up to 2.60GHz, 4T/2C, 4M Cache) On Intel Reference Platform. BIOS: v80.1 Graphics: Intel® HD Graphics (driver v. 15.36.3650) Memory: 4 GB (2x2GB) Dual Channel LPDDR3-1600 SDD: Intel® 160GB OS: Windows* 8.1 Update RTM Prior generation: Intel® Core™ i5-4302Y (up to 2.30GHz, 4T/2C, 3M Cache) on Intel Reference Platform. 4.5W Thermal Design Power. BIOS:WTM 137 Graphics : Intel® HD Graphics (driver v. 15.36.3650) Memory: 4 GB (2x2GB) Dual Channel LPDDR3-1600 SDD: Intel® 160GB OS: Windows* 8.1 Update RTM. System Power Management Policy: Balance Wireless: On and connected. Battery size assumption: 35WHr.